Market Commentary and Fund Performance

Masa Takeda of Tokyo-based SPARX Asset Management Co., Ltd., sub-advisor to the Hennessy Japan Fund, shares his insights on the Japanese market and Fund performance.

April 2024
  • Masakazu Takeda
    Masakazu Takeda, CFA, CMA
    Portfolio Manager

Performance data quoted represents past performance; past performance does not guarantee future results. The investment return and principal value of an investment will fluctuate so that an investor’s shares, when redeemed, may be worth more or less than their original cost. Current performance of the fund may be lower or higher than the performance quoted. Performance data current to the most recent month end, and standardized performance can be obtained by viewing the fact sheet or by clicking here.

Fund Performance Review

In March, the Fund returned 4.11% (HJPIX), outperforming its benchmark, the Russell/Nomura Total Market™ Index, which rose by 3.22%.

The month’s positive performers among the Global Industry Classification Standard (GICS) sectors included shares of Financials, Industrials, and Information Technology while Consumer Staples and Communication Services detracted from the Fund’s performance.

Among the best performers were our investments in Hitachi, Ltd., one of Japan’s oldest electric equipment & heavy industrial machinery manufacturers, Recruit Holdings Co., Ltd., Japan’s unique human resources and media company and the owner of U.S.-based online job advertisement subsidiary “Indeed,” and MS&AD Insurance Group Holdings, one of the leading non-life insurance companies in Japan.

As for the laggards, Nissan Chemical Corporation, a manufacturer of liquid crystal alignment films and pesticide, Seven & i Holdings Co., Ltd., a Japanese diversified retail group and operator of 7-11 convenience stores, and Rohto Pharmaceutical Co., Ltd., a leading skincare cosmetics and over-the-counter (OTC) ophthalmic medicines producer, were the largest detractors.

As previously mentioned in our letters, the Fund owns Tokyo Electron (TEL), Japan’s premier Semiconductor Production Equipment (SPE) maker. The position was initiated back in 2023 when the U.S. Commerce Department issued new export controls on semiconductor technology intended to foreclose China’s ability to obtain high-end chips as well as equipment required for manufacturing them. As the event triggered precipitous declines in semiconductor-related stocks around the world, we took it as a rare opportunity to build exposure to Japan’s semiconductor sector, which has attractive economic characteristics underpinned by the country’s long-standing manufacturing excellence.

TEL supplies critical equipment to semiconductor foundries such as TSMC, Samsung, and Intel for use in the production of semiconductor chips. It is one of the four largest SPE companies in the world along with Applied Materials (AMAT), ASML, and Lam Research. Although there are some overlaps in what they sell, each company has areas where it excels and dominates. Thus, if one of these companies were absent, there would not be advanced chips that are the building blocks of our digital society.

The chip industry will continue to be driven by the proliferation of mobile phones, PCs, 5G, and data centers as well as emerging demand from artificial intelligence, electric vehicles, and a wide range of IoT and smart devices. According to TEL’s medium-term plan released in Jun 2022, management is targeting operating profit margin (OPM) of 35% or higher and return on equity (ROE) of 30% or higher by FY2026 ending in Mar 2027. We don’t know of any other Japanese large-cap names that are in a position to aim for 30%+ ROE. Make no mistake the journey has never been in a straight line and will always fluctuate as the industry cycles are notoriously volatile, but we would be happy being an owner of a lumpy but very high ROE business rather than a smooth but mediocre ROE company.

History and the Moat

With the continuously increasing complexity of semiconductor manufacturing, the SPE industry has consolidated meaningfully over time. Manufacturing advanced semiconductors involves over 1,000 steps to create tens of billions of transistors on a chip the size of a fingernail. Correspondingly, the equipment to manufacture these chips is incredibly sophisticated, continually pushing the boundaries of engineering and physics. Each new generation of production equipment is built upon research and development (R&D) and proprietary know-how developed on prior generations of equipment, making it very difficult for a challenger to dislodge a technology leader.

SPE makers partner and collaborate with chip makers to create cutting-edge equipment based on the technology roadmap that typically extends 10+ years out. Many of the breakthrough technological advances can only be accomplished through such collaborations. For the chip makers, the risk of falling behind on the technology curve by partnering with a second tier SPE supplier is too great to bear, further cementing the position of the SPE leaders. If a defect is found during the production process, the corrective work can be extremely cumbersome and costly. The purchase manager usually does not want to take a chance with a brand-new SPE supplier that has no track record. Simply put, top-tier SPE companies are in a “high switching-cost” business.

Many of the breakthrough advances in this industry come true with persistence and perseverance through trials and errors. Fundamental R&D activities are hardly glamorous but Japanese people’s studious ethos is well-suited to this, which explains the reason why several Japanese companies hold a number one position in their respective fields ranging from silicon wafers, mask blanks, photoresists, and other specialty chemicals to SPE.

TEL’s advantage is that it has the broadest product portfolio, having four consecutive key process devices in the patterning process (deposition, coating, developing, etching and cleaning), and its market share is number one or number two in most categories. Particularly for coaters/developers, it boasts a market share of 80%+, and for the EUV (Extreme Ultraviolet) process, it has a 100% share.1

Interestingly, despite its long history since its inception in 1963, TEL, which initially began its life as a distributor for overseas semiconductor equipment, had often been viewed as a subpar SPE company with limited manufacturing/technical capabilities until the late 2000s. It was rumored that the merger plan between TEL and AMAT announced in 2013 was cancelled two years later when an extended due diligence by AMAT revealed that TEL significantly lacked R&D/technology prowess at the time.

However, the view towards TEL dramatically changed in the last decade. The seeds of change had been planted around the time of the 2008 Global Financial Crisis. During the SPE industry boom that preceded it, TEL booked record-high profits that far exceeded its previous peak. Blessed with the boom in business, TEL management rewarded its staff handsomely for their performance, which drew the envy of its peers. When the financial crisis hit and wreaked havoc on the industry, some of the weaker players were forced to scale back or even shut down their businesses entirely. As a result, TEL unexpectedly attracted chip engineers who had lost their jobs. For example, when Yokogawa Electric, a maker of industrial measurement and control equipment, pulled the plug on its semiconductor testing equipment business, its engineers joined TEL, who then went on to successfully launch the back-end process equipment business and took market share from Tokyo Seimitsu, a major rival and a former number one in wafer prober. Likewise, TEL also acquired staff from Japanese camera & precision equipment maker Nikon, who had decided to scale back their operations. TEL’s significant improvement in OPM and ROE in the subsequent decade is a testament to this strengthening of the engineering workforce. Since FY2014, TEL’s OPM rose from 14.4% to 28.0% and ROE from 11.8% to 32.0% in FY2023, while the revenue nearly quadrupled to 2.2tn yen ($14.2bn).

Product Portfolio

As the largest and most representative company within the Japanese semiconductor sector, TEL is often traded as a proxy for chip capital expenditures (capex) cycles. As such, the market view on the stock tends to mirror the industry sentiment. Recently, the sentiment has considerably recovered driven by the bottoming out of DRAM prices (which raises expectations for an upturn in the capex cycle) and generative artificial intelligence (AI)-related demand. However, our thesis is that TEL will outperform the overall capex cycle going forward owing to several new product development trends. We will discuss TEL’s product portfolio below.

Coater/Developers (26% of FY20222 equipment sales)

TEL has a whopping 89% market share here. Coaters are used to spread UV-sensitive photoresist over the entire surface of the wafer using centrifugal force from the rotation of the wafer before the lithography process (where ASML has a monopoly share). Developers are for the development process once the wafers are put through the lithography process. For EUV lithography, a method using the shortest wavelengths to produce the most advanced chips today, TEL supplies 100% of the coater/developer demand.

Etching Systems (34% of FY2022 equipment sales)

Etchers chemically remove a thin layer of the underlying material from the wafer surface to form circuit patterns following development. This is the product area where the company is currently focused on the most, and management believes that it can go on the offensive with a new product called the cryogenic etching system, which plays a key role in the fabrication of multilayer devices.

The announcement of the launch of the cryogenic etching system caught our attention when we heard that it was a hotly discussed topic and making the rounds among industry observers at the 2023 SEMICON West (a large-scale industry exhibition). According to industry sources, for 400-layer 3D-NAND fabrication,3 TEL’s new technology allows for a two-step etching process, indicating that etching rates are 2.5x faster than existing technology owned by Lam Research, with an 84% lower carbon footprint. This should sharply reduce costs at NAND makers, and TEL’s new offering has been well received by customers so far. At present, Samsung Electronics and SK Hynix are reportedly working on the production of 300+ layer 3D-NAND, and Micron and Western Digital are thought to be following suit to keep up with the race. This bodes well for TEL. Furthermore, this technology trend is expected to extend to DRAM, another type of memory chip, from around 2028 as the chip’s miniaturization effort will likely reach its limit. Beyond this point, the multi-layering of DRAM will be the primary driver (3D-DRAM), creating an additional significant business opportunity for TEL.

Looking at the process-by-process market size, etching systems are far bigger than coater/developers and even exceed lithography. It is the largest sub-segment of the SPE industry. According to Nomura,4 the etching market has outpaced other equipment markets in the past two cycles. While the overall market grew 1.77-fold from 2015 to 2018, the etching equipment market grew 1.91-fold. Similarly, while the overall market grew 1.81-fold from 2019 to 2022, the etching equipment market grew 1.91-fold. Better yet, this category is expected to continue growing rapidly as the number of layers increases in the memory chip space.  According to Mitsubishi UFJ Morgan Stanley,5 the etching equipment market could grow 50-75% if 3D-DRAM becomes mainstream. Although Lam Research ranked as the leading manufacturer as of 2022 at 50% market share, followed by TEL in second place, the cryogenic etcher may become a game changer for TEL.

Cleaning Equipment (12% of FY2022 equipment sales)

Cleaning equipment eliminates fine particles, natural oxides, and various other types of impurities using chemical solutions because any impurities on wafers result in faulty semiconductor circuits. There are two types of equipment. Batch cleaning equipment processes multiple wafers at once, while single-wafer cleaning equipment processes one wafer at a time. In both categories, Japan’s Screen Holdings is the global leader but TEL has been closing in as a second runner-up, especially in the single-wafer cleaning type. The requirements for the removal of particles and impurities have become greater, and as such the market for single-wafer cleaning equipment has been growing faster than the batch type. According to BoA research the batch type outnumbered the single-wafer type by a ratio of 6 to 4 in 2007, but the single-wafer type overtook by a ratio of 8 to 2 in 2022.6 This bodes well for continued market share gains by TEL.

Deposition Equipment (21% of FY2022 equipment sales)

Deposition systems are used to deposit a thin film of a particular material on the wafer surface as circuit materials. Different types of semiconductors require different types of circuit materials as well as different deposition processes. As such, there are more variations for deposition systems than there are for lithography and etching. TEL specializes in thermal deposition (oxide/anneal), CVD (chemical vapor deposition), ASFD (advanced sequential flow deposition), ALD (atomic layer deposition), and PVD (sputtering). Of these, ALD is a likely driver of demand going forward. Where is ALD best used? As the future generations of semiconductors are expected to adopt the GAA transistor architecture (for 2nm) and CFET (for 1nm>), the high aspect ratio structures will drastically increase the exposed surface area that needs to be deposited (in the same way a larger wall produces more space to apply a fresh coat of paint on). That’s where batch ALD technology will come into play, where Japan’s Kokusai Electric is the market leader currently. Given the track record of TEL’s market share acquisitions as a late-comer in other equipment markets, we would like to closely monitor its new product launch schedules and breakthrough technology-related announcements.

Back-End Process Equipment

The SPE makers have been historically divided between the front-end field (processes around the patterning on the wafers) and the back-end field (processes around the slicing and packaging of the finished wafers). TEL predominantly operates in the front-end domain but as explained above, has been spreading its tentacles to the back-end process equipment business such as BIST (Built-in self-tester) for flash memory and wafer probers. Elsewhere, TEL has been expanding its product lines for use in HBM (High Bandwidth Memory) production, which is in hot demand to run AI servers today. TEL’s new offerings include wafer bonders (for bonding to achieve 3D integration, which competes with Austria’s EV Group), laser edge trimming systems (for wafer thinning, which has higher trimming quality, simplified process, and eco-friendly compared to conventional technology offered by Japan’s dominant back-end dicer & grinder manufacturer Disco). In recent years, the pace of chip miniaturization is said to have been slowing as Moore’s Law nears its limit in the front-end field. As a result, the importance of chip design as well as back-end process technologies such as advanced packaging is rising to continue improving chip performance. TEL is adapting to this trend quickly.

Risks

The semiconductor and SPE industries have been cyclical in the past and are expected to continue being cyclical in the future (the industry cycles are notoriously volatile, and the related stocks are even more so). As such, we do not expect TEL’s future growth and share price move to occur on a smooth path. Furthermore, from time to time, technology shifts and advancements can make certain equipment obsolete leading to the emergence of a new equipment market.

For example, in lithography, with the wider adoption of the EUV process, Japan’s former champions in KrF/ArF steppers Canon and Nikon lost in their race against the Dutch company ASML, who now reigns as the dominant EUV lithography equipment supplier. In the other cases, competition between the existing segments of the SPE industry had led to shifts in fortunes. In the mid-2010s, shares of Lam Research marched ahead on the back of the successful commercialization of 3D-NAND, which led to a sharp increase in demand for etching systems, while other SPE makers lagged. However, after 2018, the situation reversed as the EUV process began to move into the mainstream. ASML has been thriving thanks to large order flows for its EUV scanners since then.

TEL will not be immune to these ever-changing technology trends. For TEL’s existing product lines, the current technology roadmap suggests that there is a potential risk of coaters/developers going obsolete should the industry move to dry resists from the conventional chemically amplified resists (CAR). This new type of photoresist will allow for further miniaturization of circuit patterns (should enable the shrinkage down to around 1nm) thanks to the higher sensitivity and resolution of the materials. Dry resist comes in non-liquid form, which means it is applied to the wafer surface with specialized CVD equipment (jointly developed by Lam Research, ASML and Imec), eliminating the need for TEL’s coaters/developers. That said, at this stage, complete replacement of CAR is considered a low probability scenario as the eventual throughput and defectivity of using the new resist is said to be unknown and increase the number of manufacturing steps as well as process costs.

At the end of the day, TEL’s advantage is that it has the broadest product portfolio in the SPE industry with four consecutive key process devices in the patterning process as we have seen in the above discussions. This portfolio diversifies TEL’s exposure to any particular product step or technology, reducing the overall risk profile for the business. The sheer size of the workforce attests to this strength. While large comprehensive SPE makers like TEL, AMAT, and LAM boost 17,000~34,000 strong staff, specialized equipment suppliers such as Advantest (testers), Kokusai Electric (ALD systems), Lastertec (photomask inspection systems), ASMI (deposition systems) typically employ only a few thousand (1,000~6,000).

Finally, we would like to touch on a few potential threats to the entire chip industry. First, with Moore’s Law nearing the end of the road, the growth opportunities for SPE makers driven by miniaturization may stall at some point in the future. According to Imec, a research institute for semiconductor, the current roadmap calls for 1nm> in terms of circuit line width. Logically, the minimum line width cannot be less than the size of an atom (0.1~0.5nm). Thus, it is probably safe to assume that the shrinkage of circuit patterns will come to an end once we reach sub-1nm nodes. That said, as of today there are at least 3~5 generations more to go.7 As a migration to a new node generally takes several to 10+ years, the industry should have growth runway of at least another 20 years (possibly longer).

Second is the uncertain future of China’s demand. China has been accelerating its domestic semiconductor investments to nurture home-grown champions post the 2022 U.S. sanctions. As a way to get around this, China has been aggressively placing orders for equipment for mature nodes, which falls outside of the sanctions. TEL’s sales to China have spiked this fiscal year, now accounting for 47% of total sales (FY2023Q3). So far, the stock market has reacted positively to this news but we are wary of the potential capacity overbuild, which could lead to a significant supply glut down the road.

The last conceivable risk scenario is the arrival of ground-breaking technologies like all-photonics networks and super-conductivity. Should this occur, it may or may not turn the entire chip industry on its head. For now, these Industrial Revolution-type potential game-changers are many years away and even with successful development, the commercialization phase will take years to unfold thereafter.

With all these things in mind, we will continue to follow the industry closely.

Click here for a full listing of Holdings.

1 Source: https://semi-net.com/feature/posts/cd-maskinspection.

2 Source: Company Report (fy23q4presentations-e (tel.com)).

3 NAND is a type of memory chip also known as flash. Unlike the rest of the semiconductor industry, NAND has enjoyed massive yearly cost decreases. Instead of relying on lithography for smaller patterning (major driver of logic chips miniaturizations), NAND has relied on a different architecture, 3D-NAND, first commercialized in 2013. Since then, NAND makers have improved NAND’s density and cost structure by adding more and more layers of memory cells.

4 Source: 2023 Oct Nomura Tech Monthly.

5 Source: 230901 reports.

6 Source: 14 Mar 2024 report.

7 When going from 2nm to 1nm, even though the size of reduction in absolute scale will be much smaller (shrunk only by 1nm vs 65nm when we went from 130nm to 65nm in the early to mid-2000s), the rate of improvement in chip performance should be significant because the line width is halved in both cases. That said, it seems the actual performance gains will be less pronounced than in the past. According to TSMC, its nanosheet-based N2 node (2nm) can boast a 10% to 15% higher performance at the same power and complexity as well as a 25% to 30% lower power consumption at the same frequency and transistor count when compared to TSMC’s N3E (3nm). This reference suggests that while chip miniaturization continues to provide performance improvements, the rate of these improvements will be somewhat less as we approach the 1nm scale due to a variety of factors including quantum effects, manufacturing challenges, and physical limitations of the materials used. (Source: https://www.tomshardware.com/news/tsmc-reveals-2nm-fabrication-process).